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HDLC
Table 31. HDLC AC timing specifications 1 (continued)
Characteristic
Outputs—External clock high impedance
Inputs—Internal clock input setup time
Inputs—External clock input setup time
Inputs—Internal clock input hold time
Inputs—External clock input hold time
Symbol 2
t HEKHOX
t HIIVKH
t HEIVKH
t HIIXKH
t HEIXKH
Min
1
9
4
0
1
Max
8
—
—
—
—
Unit
ns
ns
ns
ns
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t HIKHOX symbolizes the outputs
internal timing (HI) for the time t serial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
The following figure provides the AC test load.
Output
Z 0 = 50 Ω
R L = 50 Ω
OV DD /2
Figure 22. AC test load
Figure 23 and Figure 24 represent the AC timing from Table 31 . Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
The following figure shows the timing with external clock.
Serial CLK (Input)
t HEIVKH
t HEIXKH
Input Signals:
(See Note)
t HEKHOV
Output Signals:
(See Note)
t HEKHOX
Note: The clock edge is selectable.
Figure 23. AC timing (external clock) diagram
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
33
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相关PDF资料
TWR-PXN20-KIT
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